Lateral Double-Diffused (LD) transistors have been widely employed in high voltage applications. For high performance LD transistors, low drain-to-source on-resistance (Rdson) is desired to minimize its power dissipation when it is turned on, as well as high breakdown voltage to maximize its voltage capability. To achieve low Rdson, the channel of the high LD transistor should be as short as possible.
As technology evolves into era of deep sub-micron (e.g., beyond 0.35 μm) Very-Large-Scale Integration (VLSI), there is a desire for both high voltage (HV) LD transistors and low voltage (LV) transistors to be fabricated on the same substrate. Generally, the processes for forming LV devices, such as complementary metal-oxide-semiconductor (CMOS) processes, are used to form the HV devices. However, conventional CMOS processes are incompatible for forming HV transistors. For example, process overlay issues make it difficult for alignment of the HV channel well, which defines the channel length. Process variations in process overlay requires large process windows. This makes forming short channel lengths to achieve low RDson difficult if not impossible. Furthermore, the thin gate electrodes used prevent them serving as a hard mask, further exacerbating process control in forming the channel well.
From the foregoing discussion, it is desirable to provide reliable HV devices formed with short channel lengths to have low Rdson.